This application claims the benefit of Korean Patent Application No. 2001-84259, filed on Dec. 24, 2001 in Korea, which is hereby incorporated by reference for all purposes as if fully set forth herein.
1. Field of the Invention
The present invention relates to a liquid crystal display (LCD) device and more particularly, to an array substrate for In-Plane Switching (IPS) mode liquid crystal display device and fabricating method for the same in order to realize a minute pixel.
2. Discussion of the Related Art
A typical liquid crystal display (LCD) device uses optical anisotropy and polarization properties of liquid crystal molecules. The liquid crystal molecules have a definite orientation order in alignment resulting from their thin and long shapes. The alignment direction of the liquid crystal molecules can be controlled by supplying an electric field to the liquid crystal molecules. In other words, as the alignment direction of the electric field is changed, the alignment of the liquid crystal molecules also changes. Because incident light is refracted to the orientation of the liquid crystal molecules due to the optical anisotropy of the aligned liquid crystal molecules, image data is displayed.
Currently, active matrix LCDs, in which the thin film transistors and the pixel electrodes are arranged in the form of a matrix, are widely used because of their high resolution and superiority in displaying moving images. An array substrate for the related art in-plane switching (IPS) mode liquid crystal display (LCD) device and the fabricating method for the same will be described hereinafter.
FIG. 1 is a plan view of a pixel of an array substrate for a related art in-plane switching (IPS) mode liquid crystal display (LCD) device. As shown in the figure, a plurality of gate lines 12 and common lines 16 are horizontally formed on an array substrate 10 and they are spaced apart from each other. A plurality of data lines 24 is vertically formed on the array substrate 10 and cross the gate lines 12 and the common lines 16. The data line 24 defines a pixel xe2x80x9cPxe2x80x9d by crossing the gate line 12. A thin film transistor xe2x80x9cTxe2x80x9d is formed in a cross point of the gate line 12 and the data line 24. The thin film transistor xe2x80x9cTxe2x80x9d includes a gate electrode 14, an active layer 20, a source electrode 26 and a drain electrode 28. The active layer 20, the source electrode 26 and the drain electrode 28 are formed over the gate electrode 14. The gate electrode 14 communicates with the gate line 12 and the source electrode 26 communicates with the data line 24. A pixel electrode 30 that communicates with the drain electrode 28 and a common electrode 17 that is parallel with the pixel electrode 30 are formed in the pixel region xe2x80x9cPxe2x80x9d. The common electrode 17 communicates with the common line 16. The pixel electrode 30 includes an extension portion 30a, a vertical portion 30b and a horizontal portion 30c. The extension portion 30a of the pixel electrode 30 is extended from the drain electrode 28 and the vertical portion 30b of the pixel electrode 30 is vertically extended from the extension portion 30a. The horizontal portion 30c of the pixel electrode 30 is formed over the common line 16 and connected to the vertical portion 30b. The common electrode 17 includes a horizontal portion 17a and a plurality of vertical portions 17b. The plurality of vertical portions 17b of the common electrode 17 is arranged in an alternating order with the vertical portion 30b of the pixel electrode 30. The horizontal portion 17a of the common electrode 17 connects the plurality of the vertical portion 17b into one portion. An auxiliary storage capacitor xe2x80x9cCxe2x80x9d is formed in the pixel region xe2x80x9cPxe2x80x9d. The auxiliary storage capacitor xe2x80x9cCxe2x80x9d uses a portion of the common line 16 as a first storage electrode and the horizontal portion of the pixel electrode 30c as a second storage electrode.
FIGS. 2A to 2C are cross-sectional views taken along IIxe2x80x94II and IIIxe2x80x94III of FIG. 1 illustrating a fabrication process according to a fabrication sequence of the related art. In FIG. 2A, the gate line 12 of FIG. 1 including the gate electrode 14, the common line 16 and the common electrode 17 are formed on the substrate 10 by depositing and patterning conductive metal material such as aluminum (Al), aluminum neodymium (AlNd), chromium (Cr), molybdenum (Mo) or tungsten (W), for example. A gate insulating layer 18 is then formed on the substrate 10 by depositing inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiO2), for example. The active layer 20 and an ohmic contact layer 22 are formed on the gate insulating layer 18 by depositing and patterning amorphous silicon (a-Si:H) and doped amorphous silicon (n+a-Si:H or p+a-Si:H).
In FIG. 2B, the data line 24, the source electrode 26, the drain electrode 28 and the pixel electrode 30 are formed on the substrate 10 by depositing and patterning conductive metal material such as aluminum (Al), aluminum neodymium (AlNd), chromium (Cr), molybdenum (Mo) or tungsten (W), for example. The data line 24 defines the pixel region xe2x80x9cPxe2x80x9d by crossing the gate line 12 and the common line 16. The source electrode 26 is formed by being extended from the data line 24 and partially overlapped with the active layer 20. The drain electrode 28 is spaced apart from the source electrode 26. The pixel electrode 30 comprises the extension portion 30a, the vertical portion 30b and the horizontal portion 30c. The horizontal portion 30b of the pixel electrode 30 is formed on the common line 16. The active layer 20 portion between the source electrode 26 and the drain electrode 28 is exposed by etching the ohmic contact layer 22 between the source electrode 26 and the drain electrode 28.
In FIG. 2C, a passivation layer 32 is formed on the substrate 10 by coating organic insulating material such as benzocyclobutene (BCB), for example, or by depositing inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiO2), for example.
FIG. 3 is a circuit diagram of FIG. 1. A capacitor communicates with the thin film transistor xe2x80x9cTxe2x80x9d in series. The capacitor includes a liquid crystal capacitor (CLC) and a storage capacitor (CST), which is connected in parallel to the liquid crystal capacitor (CLC).
However, if the pixel structure stated above for the in-plane switching (IPS) mode liquid crystal display (LCD) device that drives a minute pixel, an area for the storage capacitor xe2x80x9cCxe2x80x9d is limited. Moreover, if the area for the storage capacitor xe2x80x9cCxe2x80x9d is designed to be larger in order to secure a capacitance of the storage capacitor xe2x80x9cCxe2x80x9d, an aperture ratio of the liquid crystal panel is decreased.
Accordingly, the present invention is directed to an array substrate for in-plane switching (IPS) mode liquid crystal display (LCD) device and method for fabricating the same that substantially obviates one or more of problems due to limitations and disadvantages of the related art.
An advantage of the present invention is to provide the array substrate for in-plane switching (IPS) mode liquid crystal display (LCD) device in order to secure enough auxiliary capacitance without enlarging an area of a storage capacitor xe2x80x9cCxe2x80x9d.
Another advantage of the present invention is to provide a fabricating method for the array substrate for in-plane switching (IPS) mode liquid crystal display (LCD) device in order to secure enough auxiliary capacitance without enlarging an area of a storage capacitor xe2x80x9cCxe2x80x9d.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, an array substrate for in-plane switching (IPS) mode liquid crystal display (LCD) device comprises a substrate having a plurality of pixel regions, a plurality of gate lines and a plurality of common lines in a horizontal direction, the common line being spaced apart from the gate line; a plurality of data lines crossing the gate line and the common line; a thin film transistor at a cross point of the gate line and the data line, the thin film transistor having a gate electrode, an active layer, a source electrode and a drain electrode; a pixel electrode having an extension portion, a vertical portion and a horizontal portion, the extension portion being extended from the drain electrode to the pixel region, the vertical portion being vertically extended from the extension portion and the horizontal portion being over the common line and being connected to the vertical portion; a common electrode having a plurality of vertical portions and a horizontal portion, the plurality of the vertical portions being vertically extended from the common line and arranged in an alternating pattern with the vertical portion of the pixel electrode, the horizontal portion connecting the plurality of the vertical portions into one portion, and an auxiliary line over the horizontal portion of the pixel electrode and being overlapped with the common line.
The array substrate further comprises a dummy line, referred to as a common guard ring, in a non-display area of the substrate that communicates with the auxiliary line in order to apply a common voltage to the auxiliary line. The gate line, the common line and the dummy line are formed one of aluminum (Al), aluminum alloy (Al alloy), tungsten (W), molybdenum (Mo), copper (Cu) and chromium (Cr). The common line and the horizontal portion of the pixel electrode having an insulating layer therebetween forms a first auxiliary storage capacitor and the horizontal portion of the pixel electrode and the auxiliary line having an insulating layer therebetween forms a second auxiliary storage capacitor.
A fabrication method of an array substrate for in-plane switching (IPS) mode liquid crystal display (LCD) device comprises forming a plurality of gate lines, a plurality of common lines and a dummy line on an array substrate, the gate line and the common line being formed in a horizontal direction and spaced apart from each other, the dummy line being formed in a non-display area; forming a plurality of data lines crossing the gate line and the common line; forming a thin film transistor at a cross point of the gate line and the data line, the thin film transistor including a gate electrode, an active layer, a source electrode and a drain electrode; forming a pixel electrode having an extension portion, a vertical portion and a horizontal portion, the extension portion being extended from the drain electrode, the vertical portion being vertically extended from the extension portion and the horizontal portion being over the common line and connected to the vertical portion; forming a common electrode having a plurality of vertical portions and a horizontal portion, the plurality of the vertical portions being vertically extended from the common line and arranged in an alternating pattern with the vertical portion of the pixel electrode, the horizontal portion connecting the plurality of the vertical portions into one portion; and forming an auxiliary line over the horizontal portion of the pixel electrode, the auxiliary line being overlapped with the common line and one end of the auxiliary line communicating with the dummy line.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.